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FUJITSU SEMICONDUCTOR DATA SHEET
DS04-28828-3E
ASSP For Screen Display Control
CMOS
On-Screen Display Controller
MB90099
s DESCRIPTION
The MB90099 is an on-screen display controller for displaying text and graphics on the TV screen. The threechannel output control function, compact package and low voltage operation make this device suitable for onscreen displays in portable devices including camera-integrated VTRs and digital still cameras. The MB90099 controls a display area of 28 characters by 12 lines, and provides 1,024 different characters, each composed of 12 x 18 dots. All 1,024 characters in font ROM can be set by the user. The display functions include a wealth of characters with qualifying functions such as character background shading (shadow casting) and individual character size setting, with 16-color display selection for each character. Also included are the line background, screen background, and sprite character functions, providing a wide variety of screen display capabilities.
s FEATURES
* Character screen configuration : * Character types : 28 characters x 12 lines (maximum) 1,024 characters (integrated in ROM, user definable through the entire area)
(Continued)
s PACKAGE
20-pin plastic SSOP 20-pin plastic FLGA
(FPT-20P-M03)
(LGA-20P-M01)
MB90099
(Continued) * Font configuration :
12 x 18 dots (font ROM comfiguration) Horizontal/vertical character display size setting enabled. Two horizontal width settings (S/L) per character. S size : 6 dots L size : 12 dots Two vertical height settings (HA/HB) per line. HA : 18 dots HB : 12 dots Character trimming : Enabled/Disabled (set for each line) Character background : None/Solid-fill/Shaded background (concave) /Shaded background (convex) (set for each character) Horizontal character merge/independent display with shaded background (set for each character) Vertical line merge/independent display with shaded background (set for each line) Character background display extended to line spacings : Enabled/Disabled (set for each line) Line background : None/Solid-fill/Shaded background (concave) /Shaded background (convex) (set for each line) (Display extends into left and right screen margins and into line spacings) Character enlargement : 4 types : Normal, Double width, Double height, Double width x double height (set for each line) Enlarged character dot interpolation function (set for each line) Horizontal display position : Control in 2-dot units (movable through the entire screen) Vertical display position : Control in 2-dot units (movable through the entire screen) Line spacing control : Control in 1-dot units (set between 0 to 7 dots for each line, applied simultaneously to two areas above and below the line) Sprite character display : Enable/Disabled Sprite character types : 256 types (character codes 000H to 0FFH) Sprite character trimming : Enabled/Disabled Sprite character configuration : 2 types : 1 character/Stack of 2 characters Sprite character horizontal display position : Control in 1-dot units (movable through the entire screen) Sprite character vertical display position : Control in 1-dot units (movable through the entire screen) Screen background color : Enabled/Disabled
* Display modes :
* Character screen display position control :
* Sprite character control :
* Screen background control :
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MB90099
* Display colors :
Character color : 16 colors (set for each character) Character trimming color : 16 colors (set for each line) Character background color : 16 colors (set for each character) * Line background color : 16 colors (set for each line) Screen background color : 16 colors Sprite character color : 16 colors Sprite character trimming color : 16 colors Shaded background frame highlight color : 16 colors Shaded background frame shadow color : 16 colors Color signal output : 4 bits (supports 16 colors) Display period signals : 3 channels (output selector circuit provided) 16-bit serial input : Chip select Serial clock Serial data SSOP-20 FLGA-20 2.4 V to 3.6 V
* Display signal output : * External interface :
* Package : * Supply voltage :
* : Character background color (color code) = "0" is transparent (displays lower-layer color) .
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MB90099
s PIN ASSIGNMENTS
(TOP VIEW)
1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 HSYNC VSYNC VC0 VC1 VC2 BLKA VC3 BLKB TESTO BLKC
SCLK CS SIN RESET VDD SDR N.C. EXD TEST GND
SSOP-20 (FPT-20P-M03)
(TOP VIEW)
CS HSYNC SCLK VSYNC
A2 A3 A4 A5 SIN RESET VDD SDR N.C. EXD B1 C1 D1 E1 F1 G1 H2 H3 H4 H5 TEST BLKC TESTO B6 C6 D6 E6 F6 G6 VC0 VC1 VC2 BLKA VC3 BLKB
GND
FLGA-20 (LGA-20P-M01)
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MB90099
s PIN DESCRIPTIONS
Pin no. SSOP FLGA 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 16 17 18 19 20 A3 A2 B1 C1 D1 E1 F1 G1 H2 H3 H4 H5 G6 E6 F6 D6 C6 B6 A5 A4 Pin name SCLK CS SIN RESET VDD SDR N.C. EXD TEST GND BLKC TESTO BLKB BLKA VC3 VC2 VC1 VC0 VSYNC HSYNC I/O I I I I I I I O O O O O O O O I I Circuit type A A A B C B C D D D D Function Shift clock input pin for serial transfer. This pin has an internal pullup resistor. Chip select pin. Input a low level signal during serial transfer. This pin has an internal pull-up resistor. Serial data input pin. This pin has an internal pull-up resistor. Reset input pin. Input a low level signal at power-on time. +3 V power supply pin. Data input direction select pin for serial transfer. Input a low level signal at LSB-first transfer mode, or a high level signal at MSB-first transfer mode. Not connected. This pin should be left open. Display dot clock input pin. LSI test input pin. Input a low level signal during normal use. Ground pin. Display period signal output pin for output channel C. LSI test output pin. This pin should be left open during normal use. Display period signal output pin for output channel B. Display period signal output pin for output channel A.
D
Color code signal output pins.
B B
Vertical synchronization signal input pin. Horizontal synchronization signal input pin.
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MB90099
s I/O CIRCUIT TYPES
Type Circuit Remarks CMOS level, hysteresis input, pullup resistance (25 k to 200 k) .
R
A
CMOS level, hysteresis input.
B
CMOS level input.
C
CMOS level output.
D
Output
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MB90099
s BLOCK DIAGRAM
SCLK CS Serial input control SIN SDR To controllers
EXD
Display control
HSYNC VSYNC
VC3 VC2 VC1 Output control Display memory (VRAM) Font ROM VC0 BLKC BLKB BLKA
TEST
Test control block
TESTO
RESET
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MB90099
s COMPONENT ELEMENTS
* Serial input control block Receives serial commands and data. Decodes commands, and allocates commands and data to the appropriate control blocks. * Display control block Performs display control functions synchronized with the input sync signals. * Display memory (VRAM) block VRAM memory for character data (24 bits x 28 characters x 12 lines) and line data (24 bits x 12 lines) . * Font ROM block ROM memory for display character fonts. Configured for 1,024 characters of 12 dots x 18 dots. * Output control block Generates output signals by applying display processing to the font data read from the font ROM. * Test control block Circuits for factory testing of the LSI before delivery.
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MB90099
s ABSOLUTE MAXIMUM RATINGS
(VGND = 0 V) Parameter Power supply voltage Input voltage Output voltage Power consumption Operating temperature Storage temperature Symbol VDD VIN VOUT Pd Ta Tstg Rating Min. VGND - 0.5 VGND - 0.5 VGND - 0.5 -20 -55 Max. VGND + 4.0 VDD + 0.5 VDD + 0.5 100 +70 +150 Unit V V V mW C C Remarks
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
s RECOMMENDED OPERATING CONDITIONS
(VGND = 0 V) Parameter Power supply voltage "H" level input voltage 1 "L" level input voltage 1 "H" level input voltage 2 "L" level input voltage 2 Operating temperature Symbol VDD VIHS VILS VIH VIL Ta Value Min. 2.4 0.8 x VDD VGND 0.7 x VDD VGND -20 Max. 3.6 VDD + 0.3 0.2 x VDD VDD + 0.3 0.3 x VDD +70 Unit V V V V V C *1 *1 *2 *2 Remarks
*1 : Input pins excluding TEST and SDR pins. *2 : TEST and SDR input pins. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
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MB90099
s ELECTRICAL CHARACTERISTICS
1. DC Characteristics
Symbol VOH VOL IIH IIL RPULL (VGND = 0 V, Ta = -20 C to +70 C) Pin name Conditions Value Min. VDD - 0.5 VGND 25 Typ. 50 Max. VDD 0.4 +10 -10 200 5 6 16 Unit V V A A k mA mA pF
Parameter "H" level output voltage "L" level output voltage "H" level input current "L" level input current Pull-up resistance
VDD = 3.3 V VC3, VC2, VC1, VC0, IOH = -4 mA BLKC, BLKB, BLKA VDD = 3.3 V IOL = 4 mA SDR, HSYNC, VSYNC, EXD, TEST, RESET SIN, SCLK, CS VDD = 3.3 V VIH = VDD VDD = 3.3 V VIL = 0 V VDD = 3.3 V VDD = 2.4 V fDC = 8 MHz VDD = 3.6 V fDC = 8 MHz
Power supply current
ICC
VDD
Input capacitance
C
Except VDD, GND
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MB90099
2. AC Characteristics
(1) Serial input timings (VDD = 2.4 V to 3.6 V, VGND = 0 V, Ta = -20 C to +70 C) Symbol tCYC tWCH tWCL tCR tCF tSS tSU tH tEC tCRC tCFC Pin name SCLK SCLK SCLK SCLK SIN CS CS Value Min. 250 100 100 100 100 50 100 Max. 200 200 200 200 Unit ns ns ns ns ns ns ns ns ns ns ns
Parameter Shift clock cycle time Shift clock pulse width Shift clock signal rise/fall time Shift clock start time Data setup time Data hold time Chip select end time Chip select signal rise/fall time
CS
0.8 VDD 0.2 VDD
0.8 VDD 0.2 VDD tCRC
tCFC
tSS
tCYC
tEC 0.8 VDD
SCLK
tCR tSU tWCH tCF tH 0.8 VDD tWCL tCR
0.2 VDD
SIN
0.2 VDD
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MB90099
(2) Vertical and horizontal sync signal input timing
(VDD = 2.4 V to 3.6 V, VGND = 0 V, Ta = -20 C to +70 C) Pin name HSYNC VSYNC HSYNC VSYNC VSYNC VSYNC VSYNC Value Min. 18 4 -6 2 2 Max. 200 200 200 200 6 1H - 4 1H - 14 20 Unit ns ns ns ns Dot clock s Dot clock Dot clock H H
Parameter Horizontal sync signal rise time Horizontal sync signal fall time Vertical sync signal rise time Vertical sync signal fall time Horizontal sync signal pulse width *1 Vertical sync signal setup time1 * (Except for VVE = 1, VHE = 1, HE = 1) *3 Vertical sync signal setup time2 *2 (VVE = 1, VHE = 1, HE = 1) *3 Vertical sync signal detection hold time Vertical sync signal pulse width
2
Symbol tHR tHF tVR tVF tWH tVS tVS tVH tWV
*1 : During the horizontal sync signal pulse period, the MB90099 stops its internal operation, disabling writing to the internal VRAM. Therefore, the horizontal sync signal pulse width and VRAM write cycle (command 2 or command 4 issuance cycle) should be set so that the horizontal sync signal pulse width is shorter than the VRAM write cycle. *2 : In the vertical sync signal detection cycle, do not change the vertical sync signal (detection edge) when it is close to the horizontal sync signal edge. This may result in distortion of the display due to fluctuations in the sync signal. *3 : VVE, VHE and HE are control bits of Command 13-0 (I/O pin control) . VSYNC : Leading-edge operation (VVE = 0) HSYNC : VSYNC detection at the trailing edge (VHE = 1)
tVF tVS tWV tVH 0.8 VDD 0.2 VDD 0.2 VDD tVR
VSYNC
0.8 VDD
tHF tWH
tHR
HSYNC
0.8 VDD 0.2 VDD
0.8 VDD 0.2 VDD
(Continued)
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MB90099
(Continued)
VSYNC : Trailing-edge operation (VVE = 1) HSYNC : VSYNC detection at the trailing edge (VHE = 1 and HE = 0)
tVR tWV tVS 0.8 VDD 0.2 VDD tVH 0.8 VDD 0.2 VDD tVF
VSYNC
tHF tWH
tHR
HSYNC
0.8 VDD 0.2 VDD
0.8 VDD 0.2 VDD
VSYNC : Leading-edge operation (VVE = 0) HSYNC : VSYNC detection at the leading edge (VHE = 0)
tVF tVS tWV tVH 0.8 VDD 0.2 VDD 0.2 VDD tVR
VSYNC
0.8 VDD
tHF tWH
tHR
HSYNC
0.8 VDD 0.2 VDD
0.8 VDD 0.2 VDD
VSYNC : Trailing-edge operation (VVE = 1) HSYNC : VSYNC detection at the leading edge (VHE = 0) or (VHE = 1 and HE = 1)
tVR tWV tVS 0.8 VDD 0.2 VDD tVH 0.8 VDD 0.2 VDD tVF
VSYNC
tHF tWH
tHR
HSYNC
0.8 VDD 0.2 VDD
0.8 VDD 0.2 VDD
Note : The above diagrams assume that I/O pin control command (command 13-0) has set the sync signal input logic control setting (SIX bit) to negative logic ("0") . However, if the positive logic setting (SIX bit = "1") is used, the H and L levels are reversed. 13
MB90099
(3) Dot clock external input timing
(VDD = 2.7 V to 3.3 V, VGND = 0 V, Ta = -20 C to +70 C) Pin name EXD EXD EXD EXD HSYNC, VSYNC VC3, VC2, VC1, VC0, BLKA, BLKB, BLKC Value Min. 112 56 48 48 24 24 13 0 7 tDD1 Max. 166 83 tDD2 45 Unit ns ns ns ns ns ns ns ns ns ns Note *1 *2 *1 *2 *3 *3 *3
Parameter Dot clock cycle time
Symbol tDCYC1 tDCYC2 tDWH1 tDWL1 tDWH2 tDWL2 tDS tDH tDD1 tDD2
Dot clock pulse time
HSYNC, VSYNC setup time HSYNC, VSYNC hold time Data output delay time 1 Data output delay time 2
Note : The above items assume a supply voltage of VDD = 2.7 V to 3.3 V. *1 : Assuming input frequency = dot clock x 1. *2 : Assuming input frequency = dot clock x 2. *3 : Assuming input frequency = dot clock x 1 or dot clock x 2.
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MB90099
tDCYC1,tDCYC2 tDWH1, tDWH2 tDWH1, tDWH2 0.8 VDD
EXD input
tDH tDS
0.2 VDD
HSYNC input VSYNC input
Sync signal detection period *
0.8 VDD 0.2 VDD tDD2 tDD1
Output undefined period (Output transition period)
0.8 VDD 0.2 VDD
Data output
AC measurement conditions C = 70 pF VOH = 0.8 VDD tr = 5 ns VOL = 0.2 VDD tf = 5 ns VIH = 0.8 VDD VIL = 0.2 VDD * : Do not vary the input sync signal during the sync signal detection period. Changes in the signal during this period may cause distortion in the display.
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MB90099
(4) Reset input timing
(VDD = 2.4 V to 3.6 V, VGND = 0 V, Ta = -20 C to +70 C) Symbol tWRST tWRSD Pin name RESET EXD Value Min. 1 5 Max. Unit s Dot clock * Note
Parameter Reset pulse width Clock input
* : Clock input is required during reset.
tWRST tWRSD 0.2 VDD
RESET
EXD
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MB90099
s DISPLAY CONTROL COMMANDS
1. Command list
Command no.
Function VRAM write address setting Character data setting 1 Character data setting 2 Line control data setting 1 Line control data setting 2 Screen output control 1A Screen output control 1B Screen output control 1C Vertical display position control Horizontal display position control Shaded background frame color control Screen background control Sprite character control 1 Sprite character control 2 Sprite character control 4 Sprite character control 5 Screen extension control
Command code/data 15 to 12 0000 11 10 9 8 7 FL 6 0 5 0 4 3 2 1 0
0 1 2 3 4 5-00 5-01 5-02 5-2 5-3
AY3 AY2 AY1 AY0
AX4 AX3 AX2 AX1 AX0
0 0 0 1 MO1 MO0 MM1 MM0 MB3 MB2 MB1 MB0 MC3 MC2 MC1 MC0 0010 0011 0100 0101 0101 0101 0101 0101 MR MS M9 M8 M7 M6 M5 M4 M3 M2 LF2 L2 M1 LF1 L1 M0 LF0 L0
LHS LW2 LW1 LW0 LFD LFC LFB LFA LF3 LDS LGS LG1 LG0 0 0 0 1 1 0 0 0 0 1 0 0 1 0 0 0 1 0 Y8 X8 LD LE LM1 LM0 0 DSP 0 0 Y4 X4 L3 0 0 0 Y3 X3
SDS UDS
OA2 OA1 OA0 OB2 OB1 OB0 OC2 OC1 OC0 Y2 X2 Y1 X1 Y0 X0
SOB BGB BLB SOC BGC BLC Y7 X7 Y6 X6 Y5 X5
6-1
0110
0
1
0
0
BH3 BH2 BH1 BH0 BS3 BS2 BS1 BS0
7-3
0111
1
1
0
0
0
0
0
0
U3
U2
U1
U0
8-0 8-1 9-0 9-1 11-0 11-2
1000 1000 1001 1001 1011
0 0 0 1 0 1
0 1 0 0 0 0
SFB SFA SF3 SF2 SF1 SF0 SC3 SC2 SC1 SC0 SD1 SD0 SM7 SM6 SM5 SM4 SM3 SM2 SM1 SM0 SY9 SY8 SY7 SY6 SY5 SY4 SY3 SY2 SY1 SY0 SX9 SX8 SX7 SX6 SX5 SX4 SX3 SX2 SX1 SX0 0 0 0 0 0 0 EG0 0 0 0 0 0 0 0 0 0 0
Dot clock control 1 1 0 1 1
DC2 DC1 DC0
(Continued)
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MB90099
(Continued)
Command no.
Function I/O pin control Horizontal blanking control 1 Horizontal blanking control 2
Command code/data 15 to 12 1101 1101 1101 11 0 0 1 10 0 1 0 9 8 7 HE 0 6 0 0 5 SIX 4 0 3 0 2 0 1 0 VVE VHE 0 0 0 DBX DCX
13-0 13-1 13-2
BB5 BB4 BB3 BB2 BB1 BB0
BF8 BF7 BF6 BF5 BF4 BF3 BF2 BF1 BF0
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MB90099
2. Command Description
* Command 0 (VRAM write address setting) Command 0 sets the write address in VRAM, and controls the execution of "VRAM fill". The write address is specified by row and column addresses. VRAM fill is activated by executing character data setting 2 (command 2) . 15 0 14 0 13 0 12 0 11 10 9 8 7 FL 6 0 5 0 4 3 2 1 0
AY3 AY2 AY1 AY0
AX4 AX3 AX2 AX1 AX0
AY3 to AY0 : Row address (0 to BH) AX4 to AX0 : Column address (0 to 1BH) FL : VRAM Fill control (0 : OFF, 1 : ON) * Command 1 (Character data setting 1) Command 1 specifies character data. The character data is written to VRAM and reflected on the screen by the execution of command 2 (character data setting 2) . 15 0 14 0 13 0 12 1 11 10 9 8 7 6 5 4 3 2 1 0
MO1 MO0 MM1 MM0 MB3 MB2 MB1 MB0 MC3 MC2 MC1 MC0
MO1, MO0 : Character output control MM1, MM0 : Character background control (0, 0 : Off) (0, 1 : Solid fill) (1, 0 : Concaved shaded) (1, 1 : Convexed shaded) MC3 to MC0 : Character color (16 colors) MB3 to MB0 : Background color (16 colors) * Command 2 (Character data setting 2) Command 2 writes additional character data to the location in VRAM spacified by command 0 (VRAM write address setting ),along with the character data set by command 1 (character data setting 1). The VRAM write address is automatically incremented after command 2 is executed. 15 0 14 0 13 1 12 0 11 MR 10 MS 9 M9 8 M8 7 M7 6 M6 5 M5 4 M4 3 M3 2 M2 1 M1 0 M0
MR : Shaded background succeeding character merge control (0 : Not merged with succeeding character) (1 : Merged with succeeding character) MS : Character horizontal size control (0 : S size, 6 dots) (1 : L size, 12 dots) M9 to M0 : Character code
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MB90099
* Command 3 (Line control data setting 1) Command 3 specifies line control data. The line control data is written to VRAM and reflected on the screen by the execution of command 4 (line control data setting 2) . 15 0 14 0 13 1 12 1 11 10 9 8 7 6 5 4 LFA 3 LF3 2 LF2 1 LF1 0 LF0
LHS LW2 LW1 LW0 LFD LFC LFB
LHS : Line character vertical size type control (0 : Character vertical size A) (1 : Character vertical size B) LW2 to LW0 : Line spacing control (0 to 7 dots, in 1-dot units) LF3 to LF0 : Trimming color (16 colors) LFD, LFC : Trimming output control (0, 0 : All Off) (0, 1 : Trimming On for a character only, no character background) (1, 0 : Trimming On for a solid-fill character or no character background) (1, 1 : All On) LFB, LFA : Trimming control (0, 0 : Trimming Off) (0, 1 : Reserved (setting prohibited) ) (1, 0 : Reserved (setting prohibited) ) (1, 1 : Eight-direction trimming) * Command 4 (Line control data setting 2) Command 4 specifies additional line control data and writes this data, along with the line control data set by command 3 (line control data setting 1) to the row address in VRAM specified by command 0 (VRAM write address setting) . Executing this command will not alter the VRAM write address. 15 0 14 1 13 0 12 0 11 10 9 8 7 LD 6 LE 5 4 3 L3 2 L2 1 L1 0 L0
LDS LGS LG1 LG0
LM1 LM0
LDS : Line character output control (control of a character + trimming + character background) (0 : Off, 1 : On) LGS : Line enlargement interpolation control (0 : Off, 1 : On) LG1, LG0 : Line enlargement control (0, 0 : Normal) (0, 1 : Double width) (1, 0 : Double height) (1, 1 : Double width x double height) LE : Character background extension control (0 : Normal, 1 : Extended) LD : Shaded background succeeding line merge control (0 : Independent) (1 : Merged with succeeding line)
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MB90099
LM1, LM0 : Line background control (0, 0 : Off) (0, 1 : Solid fill) (1, 0 : Concaved shaded) (1, 1 : Convexed shaded) L3 to L0 : Line background color (16 colors) * Command 5-00 (Screen output control 1A) Command 5-00 controls screen display output. 15 0 14 1 13 0 12 1 11 0 10 0 9 0 8 0 7 6 5 0 4 DSP 3 0 2 1 0
SDS UDS
OA2 OA1 OA0
SDS : Sprite character output control (0 : Off, 1 : On) * UDS : Screen background output control (0 : Off, 1 : On) * DSP : Display output control (Control of a character + trimming + character background + line background) (0 : Off, 1 : On) * OA2 to OA0 : Output-A character control (8 types) * : Input of an 'L' level signal to the RESET pin will initialize SDS = 0, UDS = 0, and DSP = 0. * Command 5-01 (Screen output control 1B) Command 5-01 controls output-B screen display output. 15 0 14 1 13 0 12 1 11 0 10 0 9 0 8 1 7 6 5 4 0 3 0 2 1 0
SOB BGB BLB
OB2 OB1 OB0
SOB : Output-B sprite character output control (0 : Off, 1 : On) BGB : Output-B screen background output control (0 : Off, 1 : On) BLB : Output-B line background output control (0 : Off, 1 : On) OB2 to OB0 : Output-B character control (8 types)
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MB90099
* Command 5-02 (Screen output control 1C) Command 5-02 controls output-C screen display output. 15 0 14 1 13 0 12 1 11 0 10 0 9 1 8 0 7 6 5 4 0 3 0 2 1 0
SOC BGC BLC
OC2 OC1 OC0
SOC : Output-C sprite character output control (0 : Off, 1 : On) BGC : Output-C screen background output control (0 : Off, 1 : On) BLC : Output-C line background output control (0 : Off, 1 : On) OC2 to OC0 : Output-C character control (8 types) * Command 5-2 (Vertical display position control) Command 5-2 controls the vertical display position on the screen. 15 0 14 1 13 0 12 1 11 1 10 0 9 0 8 Y8 7 Y7 6 Y6 5 Y5 4 Y4 3 Y3 2 Y2 1 Y1 0 Y0
Y8 to Y0 : Vertical display position control (0 to 1022 in 2-dot units) * Command 5-3 (Horizontal display position control) Command 5-3 controls the horizontal display position on the screen. 15 0 14 1 13 0 12 1 11 1 10 1 9 0 8 X8 7 X7 6 X6 5 X5 4 X4 3 X3 2 X2 1 X1 0 X0
X8 to X0 : Horizontal display position control (0 to 1022 in 2-dot units) * Command 6-1 (Shaded background frame color control) Command 6-1 controls the frame color of the shaded background. 15 0 14 1 13 1 12 0 11 0 10 1 9 0 8 0 7 6 5 4 3 2 1 0
BH3 BH2 BH1 BH0 BS3 BS2 BS1 BS0
BH3 to BH0 : Shaded background frame highlight color (16 colors) BS3 to BS0 : Shaded background frame shadow color (16 colors) * Command 7-3 (Screen background control) Command 7-3 controls the screen background color. 15 0 14 1 13 1 12 1 11 1 10 1 9 0 8 0 7 0 6 0 5 0 4 0 3 U3 2 U2 1 U1 0 U0
U3 to U0 : Screen background color (16 colors)
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MB90099
* Command 8-0 (Sprite character control 1) Command 8-0 controls sprite characters. 15 1 14 0 13 0 12 0 11 0 10 0 9 8 7 6 SF2 5 SF1 4 3 2 1 0
SFB SFA SF3
SF0 SC3 SC2 SC1 SC0
SFB, SFA : Sprite character trimming control (0, 0 : Trimming Off) (0, 1 : Reserved) (1, 0 : Reserved) (1, 1 : Eight-direction trimming) SF3 to SF0 : Sprite character trimming color (16 colors) SC3 to SC0 : Sprite character color (16 colors) * Command 8-1 (Sprite character control 2) Command 8-1 controls sprite characters. 15 1 14 0 13 0 12 0 11 0 10 1 9 8 7 6 5 4 3 2 1 0
SD1 SD0 SM7 SM6 SM5 SM4 SM3 SM2 SM1 SM0
SD1, SD0 : Sprite character configuration control (0, 0 : 1 character) (0, 1 : Reserved (setting prohibited) ) (1, 0 : Stack of 2 characters) (1, 1 : Reserved (setting prohibited) ) SM7 to SM0 : Sprite character code (000H to 0FFH for 256 different characters) * Command 9-0 (Sprite character control 4) Command 9-0 controls the vertical display position of sprite characters. 15 1 14 0 13 0 12 1 11 0 10 0 9 8 7 6 5 4 3 2 1 0
SY9 SY8 SY7 SY6 SY5 SY4 SY3 SY2 SY1 SY0
SY9 to SY0 : Sprite character vertical display position control (0 to 1023 in 1-dot units) * Command 9-1 (Sprite character control 5) Command 9-1 controls the horizontal display position of sprite characters. 15 1 14 0 13 0 12 1 11 1 10 0 9 8 7 6 5 4 3 2 1 0
SX9 SX8 SX7 SX6 SX5 SX4 SX3 SX2 SX1 SX0
SX9 to SX0 : Sprite character horizontal display position control (0 to 1023 in 1-dot units)
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MB90099
* Command 11-0 (Screen extension control) (Reserved) 15 1 14 0 13 1 12 1 11 0 10 0 9 0 8 0 7 0 6 EG0 5 0 4 0 3 0 2 0 1 0 0 0
EG0 : (Reserved) (0 : Normal) (1 : Reserved (setting prohibited) ) * Command 11-2 (Dot clock control 1) Command 11-2 controls dot clock selection. 15 1 14 0 13 1 12 1 11 1 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 1 0
DC2 DC1 DC0
DC2 to DC0 : Dot clock selection control (0, 1, 0) : External dot clock input (0, 1, 1) : Frequency-doubled external dot clock input * Command 13-0 (I/O pin control) Command 13-0 controls I/O pin functions. 15 1 14 1 13 0 12 1 11 0 10 0 9 8 7 HE 6 0 5 SIX 4 0 3 0 2 0 1 0
VVE VHE
DBX DCX
VVE : Edge selection for vertical synchronization detection*1 (0 : Leading edge, 1 : Trailing edge) VHE : HSYNC edge selection for vertical synchronization detection*1 (0 : Leading edge, 1 : Trailing edge) HE : Edge selection for horizontal synchronization operation*1 (0 : Trailing edge, 1 : Leading edge) SIX : Logic control for sync signal input (0 : Negative logic, 1 : Positive logic) DCX : Logic control for display color signal output (0 : Positive logic, 1 : Negative logic) *2 DBX : Logic control for display output period signal (0 : Positive logic, 1 : Negative logic) *2
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MB90099
*1 : When it is set up VVE = 1, VHE = 1 and HE = 1, the vertical sync detection HSYNC edge is the standard of "Leading edge". VVE VHE HE Contents of vertical sync detection Position of vertical sync detection* 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Detection of VSYNC Leading edge Detection of VSYNC Leading edge Detection of VSYNC Leading edge Detection of VSYNC Leading edge Detection of VSYNC Trailing edge Detection of VSYNC Trailing edge Detection of VSYNC Trailing edge Detection of VSYNC Trailing edge HSYNC Leading edge HSYNC Leading edge HSYNC Trailing edge HSYNC Trailing edge HSYNC Leading edge HSYNC Leading edge HSYNC Trailing edge HSYNC Leading edge + 10 clock
* : If there is the change of level for direction of VSYNC pin signal detection in the vicinity of vertical sync detection, it may occur disorder in the display (deflection of vertical direction) . Input the meaningful edge of VSYNC signal without this position of vertical sync detection. *2 : Input of an 'L' level signal to the RESET pin will initialize DCX = 0, and DBX = 0.
* Command 13-1 (Horizontal blanking control 1) Command 13-1 controls the back porch of the horizontal blanking function. 15 1 14 1 13 0 12 1 11 0 10 1 9 0 8 0 7 0 6 0 5 4 3 2 1 0
BB5 BB4 BB3 BB2 BB1 BB0
BB5 to BB0 : Back porch control (0 to 126, in 2-dot units) * Command 13-2 (Horizontal blanking control 2) Command 13-2 controls the front porch of the horizontal blanking function. 15 1 14 1 13 0 12 1 11 1 10 0 9 0 8 BF8 7 BF7 6 BF6 5 BF5 4 BF4 3 BF3 2 BF2 1 BF1 0 BF0
BF8 to BF0 : Front porch control (0 to 1022, in 2-dot units)
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MB90099
3. Notes on Issuing Commands
(1) Initialization When a reset signal is input ("L" level signal input to the RESET pin) , the MB90099 enters display-off state(*). The contents of VRAM (the character RAM and the line RAM) are undefined. Immediately after release of the input signal to the MB90099, issue the following commands to initialize control operation. * Dot clock control 1 (command 11-2) * I/O pin control (command 13-0) This must be done before setting all command data and all RAM contents. (VRAM settings require normal dot clock input and normal sync signal input.) * : The reset input initializes control bits as follows. Screen output control 1A (command 5-00) SDS = 0 Sprite Off UDS = 0 Screen background Off DSP = 0 Character, character background, line background Off I/O pin control (command 13-0) DCX = 0 VC0, VC1, VC2, VC3 pins set to positive logic output DBX = 0 BLKA, BLKB, BLKC pins set to positive logic output (2) Command refresh Command data to the MB90099 and the contents of internal VRAM are stored as long as power is supplied to the MB90099. However, there may be cases in which the serial control, sync, or dot clock signals become abnormal due to causes such as external noise, preventing the internal registers and VRAM from being set properly. It is therefore recommended that all command data and VRAM data be refreshed periodically to ensure that this data is correct. (3) Command issue timing When any control command, including a VRAM write command such as a character data setting or line control data setting command is issued, the command is executed immediately and the result is reflected on the screen. When such a command is issued during a display period, the display in the relevant field may experience momentary distortion. To avoid this, it is recommended that commands be issued during the vertical blanking interval. However that with a command 5-00 (screen output control 1A) in which one or more of the DSP, SDS, or UDS control bits is switched from OFF to ON, the display will wait until the next vertical sync signal after the command is issued and the display will start from the top of the scanning field.
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MB90099
s CONTENTS OF MB90099-001 (STANDARD PRODUCT) FONT DATA
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MB90099
28
MB90099
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MB90099
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MB90099
s FONT DEVELOPMENT AND DATA RELEASE
The MB90099 features the font ROM in which all 1024 characters are user-definable. For font data development, use the OSDC pattern editor Ped/Win. Ped/Win is an OSCD proprietary pattern editor for use on personal computers operating Windows95/98/NT4.0 (Japanese language) environments. The font development and data release flow is illustrated below.
Font development input
OSCD pattern editor Install Ped/Win Run (supplied by FUJITSU) Personal computer (Windows95/98/NT)
Pattern printing Printer
Project file
Pattern file
3-point data extraction for data release Mask data specification writing
Font data release (register with FUJITSU)
(1) Font data release Font data is released in project files only. Pattern files should not be released. A portion of the pattern file data will be used for data matching in order to verify registration of release data by FUJITSU. For this reason, users are requested to write a portion of the pattern data content in mask data specifications. Note : Pattern data output should not be generated until after the completion of font creation and project creation. Also, the project file should not be updated after pattern file generation is completed. If the project contents are updated after pattern file generation, pattern files should be generated again. (2) Project files After font data and other supplementary data is created, it is stored in a project file. Normally one project file is created for each model. * Project file names Project file names should be in the format "MB90099-XXX" where "XXX" is a ROM number assigned by FUJITSU. Users should contact their FUJITSU sales representative. If no ROM number has been assigned, any number preceded by an alphabetic character may be used. Project files which are developed solely for test purposes and not intended for font release may be assigned any file name. * Comments related to new project files Comment lines in the form of any desired character strings may be added at the time a project file is created. Comments will be printed when the font is printed, and can be modified as needed whenever that Ped/Win is operating.
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MB90099
(3) Pattern files Font data may be placed in pattern files. Because pattern data is saved in the project file, normally it is only necessary to create a pattern file at the time of font release for the purpose of extracting verification data (writing to mask data specifications) . Pattern files should not be released. * Pattern file loading Pattern files can be loaded for some OSCD models other than the MB90099. * Pattern file output generation Do not create more than one pattern file for the same project. This may cause errors . In such cases, the project name should be altered to create another project. * Extracting verification data Three data points, the first and last addresses and one other random address, should be extracted from pattern file data and written into the mask data specifications. The random address should not include the data values "00" or "FF." Note : Ped/Win display functions are based on OSDC specifications, however some display specifications may not be identical to actual OSDC specifications. Users should consult specification documents for details. (Data comparison) After data release, once ROM mask processing is completed FUJITSU will extract the ROM data used in this process. Users should verify that the extracted data is identical to the pattern file data that was submitted, and return a written statement of data comparison indicating whether that data is identical or not . If the data is not identical, contact FUJITSU's sales representative immediately. Data errors may cause errors in ES production.
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MB90099
s ORDERING INFORMATION
Part Number MB90099PFV MB90099LGA Package 20-pin Plastic SSOP (FPT-20P-M03) 20-pin Plastic FLGA (LGA-20P-M01) Remarks
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MB90099
s PACKAGE DIMENSION
20-pin Plastic SSOP (FPT-20P-M03)
* 6.500.10(.256.004)
20 11
* : These dimensions do not include resin protrusion.
0.170.03 (.007.001)
* 4.400.10
INDEX
6.400.20 (.173.004) (.252.008)
Details of "A" part 1.25 -0.10 .049 -.004 LEAD No.
1 10
+0.20 +.008
(Mounting height)
0.65(.026)
"A" 0.240.08 (.009.003) 0.13(.005)
M
0~8 0.100.10 (Stand off) (.004.004) 0.25(.010)
0.10(.004)
0.500.20 (.020.008) 0.45/0.75 (.018/.030)
C
1999 FUJITSU LIMITED F20012S-3C-5
Dimensions in mm (inches)
(Continued)
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MB90099
(Continued) 20-pin plastic FLGA (LGA-20P-M02)
4.55(.179) 5.50(.217) 3.25(.128) 0.65 (.026) 6 5 4.00(.157) 3.25(.128) 4 3 2 1 H G F E D C B A 0.45(.018) INDEX AREA 1.30(.051) Max. 20-o0.35(20-o.014) 3-o0.45(4-o.018) 0.45(.018)
0.08(.003)
C
2001 FUJITSU LIMITED L20001S-c-1-1
Dimensions in mm (inches)
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MB90099
FUJITSU LIMITED
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
F0202 (c) FUJITSU LIMITED Printed in Japan

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